One of the biggest tech news stories of the year

[RAMA]

Almost quietly...the 6th paradigm of computer processing is here: http://www.micron.com/products/hybrid-memory-cube

Of course this is the tip of the iceberg, other promising processing technologies are still developing. Just goes to show you how even "experts' can be wrong(ie:Paul Allen).

RAMA

[FordSVT]

It's "almost quietly" because it will still be a while before they are available for commercial applications, and it will likely be about 5-6 years before a product cheap enough to find its way into your home is available. If this was available in the next gen Intel processors six months from now it would be bigger news. This technology also hasn't been standardized yet, and there are other consortia developing similar technologies to compete with it.

Very cool though, yes. The processor applications interest me more than the straight up memory applications.

[RAMA]

FordSVT wrote:

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It's "almost quietly" because it will still be a while before they are available for commercial applications, and it will likely be about 5-6 years before a product cheap enough to find its way into your home is available. If this was available in the next gen Intel processors six months from now it would be bigger news. This technology also hasn't been standardized yet, and there are other consortia developing similar technologies to compete with it.

Very cool though, yes. The processor applications interest me more than the straight up memory applications.

Nope a commercial version is due next year...by guess who...Intel.

http://www.pcmag.com/article2/0,2817,2384897,00.asp

RAMA

[Chaos Descending]

Errr... no. The tri-gate 3-D transistor is not the same thing as Micron's hybrid memory cube.

[Psion]

As exciting as this news is, I can remember articles in Byte magazine discussing breakthroughs in page-oriented holographic memory promising terabytes of data on a microscope-slide-sized storage medium.

Then there were the SED display technologies which promised superior image quality to LCDs with far lower power requirements than plasma.

There are a lot of barriers, apparently, between the initial proof-of-concept and a successfully-marketed product.

[FordSVT]

Psion wrote:

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Then there were the SED display technologies which promised superior image quality to LCDs with far lower power requirements than plasma.

There are a lot of barriers, apparently, between the initial proof-of-concept and a successfully-marketed product.

The barrier to SED was primarily lawsuit after lawsuit after lawsuit. By that my the time SED was ready for prime-time, LCD televisions were selling of for chump change compared to what they'd have to launch them at. Combine that with a shitty economy in 08-09 and a nervous Canon and SED for the home was doomed. They're still developing it for commercial and professional use, however, the display technology really is superior.

But yes, a barrier is a barrier. Just because a technology looks promising now, doesn't mean something unexpected won't happen to dash the best laid plans.

[Robert Maxwell]

I'll believe it when I can buy it from Newegg!

But I will be very glad to see more breakthroughs in computer memory. We've been using more or less the same DRAM technology for, what, 30 years now?

[RAMA]

Chaos Descending wrote:

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Errr... no. The tri-gate 3-D transistor is not the same thing as Micron's hybrid memory cube.

The memory cube will exponentially increase computer performance...not just by double but much more than that.

RAMA

[RAMA]

Maxwell House wrote:

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I'll believe it when I can buy it from Newegg!

But I will be very glad to see more breakthroughs in computer memory. We've been using more or less the same DRAM technology for, what, 30 years now?

These will start out by being 15x faster right out of the gate!!!!

[Robert Maxwell]

But does that speed increase include the bus, or just the memory's internal speed? Bus speeds have always been the bottleneck between CPU and RAM.

[Lindley]

Maxwell House wrote:

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But does that speed increase include the bus, or just the memory's internal speed? Bus speeds have always been the bottleneck between CPU and RAM.

If this tech could be applied to GPUs, then internal memory speed would be more important. GPUs can easily bottleneck on memory speed. Of course, bus speed is an important fact there as well, but not the only one.

[Robert Maxwell]

Lindley wrote:

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If this tech could be applied to GPUs, then internal memory speed would be more important. GPUs can easily bottleneck on memory speed. Of course, bus speed is an important fact there as well, but not the only one.

I hadn't thought of the implications for video memory, but you're right, this would be a huge deal there, even if the system bus isn't any faster. Given the exponential increase in texture sizes over the past several years, being able to do fast operations on in-memory textures will only become more important in the future. Making the memory faster should also free up GPU time for other tasks.

[Lindley]

GPUs are increasingly being used for non-graphics computation as well.

[PurpleBuddha]

Maxwell House wrote:

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But does that speed increase include the bus, or just the memory's internal speed? Bus speeds have always been the bottleneck between CPU and RAM.

Plenty of advances have been made by Intel and AMD passing the front side bus right by:

Wiki

The front-side bus was criticized by AMD as being an old and slow technology that limits system performance.[8] More modern designs use point-to-point connections like AMD's HyperTransport and Intel's QuickPath Interconnect (QPI).[9] FSB's fastest transfer speed was 1.6 GT/s, which provided only 80% of the theoretical bandwidth of a 16-bit HyperTransport 3.0 link as implemented on AM3 Phenom II CPUs, only half of the bandwidth of a 6.4 GT/s QuickPath Interconnect link, and only 25% of the bandwidth of a 32-bit HyperTransport 3.1 link. In addition, in an FSB-based architecture, the memory must be accessed via the FSB. In HT- and QPI-based systems, the memory is accessed independently by means of a memory controller on the CPU itself, freeing bandwidth on the HyperTransport or QPI link for other uses.

This is always how things advance. typically one portion of computer system will advance forward causing other portions to bottle neck until they too advance. They drive each other forward.